1. Field of the Invention
This invention relates to digital data synthesis (DDS) of analog waveforms and more specifically to a digital waveform generator and method for synthesizing periodic analog waveforms using table readout of simulated delta-sigma (.DELTA..SIGMA.) analog-to-digital conversion data.
2. Description of the Related Art
Waveform generators are used extensively in transmitters and receivers in audio, radar, satellite and cellular telephone communications systems as well as in other applications such as calibration and test systems. The generation of stable, accurate and high resolution periodic analog waveforms over a wide frequency range is critical to the performance of these systems. For example, a high frequency carrier signal, e.g. a sinewave, is modulated by an information signal for transmission over a communications channel. At the other end of the channel, the same sinewave is used to demodulate the signal. Any distortion in the sinewaves induces distortion in the received information signal.
Known waveform generators are implemented with both analog and digital architectures. The analog waveform generators use crystal oscillators to generate the fundamental sinewaves and then synthesize the different sinewaves to produce a desired waveform. Current analog generators can produce waveforms up to approximately 100 GHz, but the signal-to-noise ratio (SNR) is poor due to harmonics and distortion. Any arbitrary frequency can be generated from DC to 100 GHz, but extensive feedback circuitry is required to control the frequency stability of the waveforms.
Known digital waveform generators store samples of a desired periodic analog waveform as N-bit codewords in a high speed memory. Typically, samples for one or more periods of the desired waveform are stored and read out cyclically to generate an N-bit digital waveform. An N-bit DAC converts the successive codewords into an analog waveform having 2.sup.N discrete levels. The waveform is then passed through a smoothing filter to generate the synthesized periodic waveform.
The quality of the synthesized waveform depends on the DAC's clock speed and bit rate. Current high speed fabrication technologies such as indium phosphide (InP) or gallium arsenide (GaAs) provide a maximum clock speed of approximately 1 GHz with 12-14 bits of resolution. The DAC's voltage levels must be allowed to settle and their ratios must be matched exactly to avoid introducing distortion into the analog waveform. This is difficult to accomplish, and thus has the effect of limiting the DAC's performance. Current digital synthesizers are capable of generating waveforms with about 10 bits of resolution at frequencies up to approximately 200 MHz to 300 MHz.
To read out the codewords at the DAC's clock speed, the memory has to be implemented in the same high speed technology as the N-bit DAC. Historically high speed technologies typically have a relatively low level of circuit integration. As a result, high speed memory is at a premium in terms of chip space and cost. Current research is directed at increasing the storage efficiency of the waveform to reduce the amount of memory required. For example, one-quarter of a period may be read out and reflected about different axis' of symmetry to regenerate a full period. In addition, the high speed readout of the N-bit codewords produces a significant amount of thermal energy that must be dissipated in the waveform generator.
In a digital generator, the frequency of the analog waveform can be changed by simply reading out the codewords faster or slower. Thus, many different sinewave frequencies can be generated by storing a fraction of the period and varying the readout rate. Due to the premium placed on memory, this is an important feature of known digital generators.
In the related fields of analog-to-digital (A/D) and digital-to-analog (D/A) real-time data conversion, delta-sigma (.DELTA..SIGMA.) modulation has been used in place of the conventional N-bit ADCs or DACs to improve the SNR of the converted signal. "Mixed-Signal Design Seminar," Analog Devices, Inc. Section VI:1-24, 1991 discloses a .DELTA..SIGMA. modulator that utilizes oversampling and noise shaping to increase the SNR of the converted signal. The .DELTA..SIGMA. modulator includes a comparator and a filter in a feedback loop. The comparator digitizes an input signal at a very low resolution, typically 1-bit, at a very high sampling rate relative to the signal frequency. Oversampling expands the bandwidth so that the signal spectrum occupies only a portion of the total bandwidth. The filter shapes the comparator's otherwise uniform quantization noise spectrum so that the bulk of the quantization noise occurs outside the signal spectrum. As a result, the SNR in the signal spectrum is increased dramatically with respect to a comparable N-bit ADC or DAC.
A .DELTA..SIGMA. DAC includes a digital interpolation filter that increases the sampling rate of the N-bit digital input signal. The sampling rate of a voiceband signal having a bandwidth of 4 kHz and an initial sampling rate of 8 kHz may be increased by a factor of 128 to a sampling rate of 1.024 MHz. The .DELTA..SIGMA. modulator noise-shapes the 16-bit 1.024 MHz data stream and reduces the sample width to 1-bit. Unlike the .DELTA..SIGMA. modulator in the .DELTA..SIGMA. ADC, this modulator is all digital although it performs the same function. A 1-bit DAC converts the serial bit stream into a binary analog signal, does not have the mismatch problems associated with higher resolution DACs and can be clocked at much higher rates.
The DAC's output is meaningless until it is averaged in some manner. An analog filter, whose characteristics are matched to the modulator's filter characteristics, averages the binary analog signal and thereby reduces the signal's bandwidth to the 4 kHz bandwidth of the voiceband signal and rejects the shaped quantization noise. The .DELTA..SIGMA. DAC produces a higher resolution analog signal than would a direct N-bit DAC. For example, using a 16-bit digital input signal, the .DELTA..SIGMA. DAC produces an analog signal having approximately 20 bits of resolution.
A principal drawback to .DELTA..SIGMA. modulators is that they are computationally intense, and hence quite slow. Using current technology, the maximum clocking speed of a .DELTA..SIGMA. DAC is approximately 10 MHz, which limits signal bandwidths to approximately 300 KHz with effectively 16 bits of resolution. Higher order .DELTA..SIGMA. modulators can be used to improve the SNR, but the additional logic circuitry required further reduces speed. Secondarily, any hardware implementation introduces some distortion into the signal due to the fixed register lengths used to perform the mathematical operations, delays and non-linearities in transistor performance.
Computer programs for simulating the .DELTA..SIGMA. modulation process are well known in the art and commonly used to design .DELTA..SIGMA. modulators for DACs. The designer can vary the modulator's parameters such as filter type (low pass or band pass) and order, register lengths, bit-rate, delay elements and clock frequency for a given N-bit input signal resolution and then simulate the results. The hardware implementations of .DELTA..SIGMA. modulators are complicated, and thus extensive simulations are often required to find an architecture that achieves the desired SNR performance.
To provide a standard against which the actual performance can be measured, the designer can switch the program to an ideal mode, in which those parameters associated with the .DELTA..SIGMA. modulator's practical limitations are set to their ideal values. For example, the registers, which are typically 14 bits, can be set to the floating point accuracy of the computer running the simulation. Boser et al. "Simulating and testing oversampled analog to digital converters," IEEE Transactions on Computer Aided Design, Vol. CAD-7, pp. 668-674, June 1988 discloses the theory behind one such program, which is commonly referred to as "Midas." The operational details for the Midas program are provide by Louis A. Williams et al., Stanford University, Version 2.1, 1990.
Because of their extremely low bandwidth, .DELTA..SIGMA. modulators have not been used in digital waveform generators, but have been limited to the conversion of real-time data for signal bandwidths below 300 KHz. If a .DELTA..SIGMA. modulator were used to read out and convert the N-bit codewords into the synthesized waveform, the distortion performance would improve but the maximum waveform frequency would be limited by the modulator. Such a waveform generator would have minimal practical utility.
Furthermore, the .DELTA..SIGMA. modulator generates a different sequence of 1s and 0s for each frequency. Thus, multiple waveforms cannot be generated from the samples of a single stored waveform. Furthermore, the reflection algorithms for improving storage efficiency are not applicable to .DELTA..SIGMA. modulation. Therefore, a full period of each desired waveform would have to be stored.